1. Field of the Invention
The present invention relates to a card interface technology relating to a host device applicable to various cards such as a SD (Secure Digital) card.
2. Description of the Related Art
Some digital devices are provided with a recording function and a reproducing function for various contents data, for example, audio, music, still image, moving image and the like. Hereinafter, the digital device thus constituted is referred to as a host device. Examples of the host device are a digital video camera, digital camera, laptop personal computer (PC), PDA (Personal Digital Assistants), mobile telephone, digital television, DVD recorder, DVD player, printer, copying machine, and the like.
There are an increasing number of host devices provided with a card interface which allows various contents data to be read from and written in a detachable small-size recording medium. As the digital device is increasingly miniaturized in recent years, the small-size recording medium installed therein is also increasingly miniaturized. As a result, a generally called memory card in which a semiconductor memory is used as a recording medium further miniaturized is often adopted today. Among all of the memory cards thus constituted, a large number of SD cards in compliance with the SD standards have been made commercially available as a memory card which supports the protection of a copyright. The SD card is a memory device in which information is memorized in a semiconductor memory chip provided therein. The SD card directly and electrically accesses a nonvolatile memory formed in the semiconductor memory chip to read data therefrom and write data therein. The SD card, which is thus free of any mechanical control, can write and read data faster than other memory devices and has a size and a weight which are relatively small.
Referring to FIG. 10, the host device which reads data from the SD card thus constituted is described. A host device 1 comprises a reference clock generator 3, and sends a reference clock generated by the reference clock generator 3 to a SD card 2 via a buffer (driver) 4 as a read clock. In response to the input of the read clock to a clock input terminal of a D flip-flop 6 via a buffer (receiver) 5, the SD card 2 sends data inputted to an input terminal D of the D flip-flop 6 (read data) to a buffer 8 of the host device 1 via an output terminal Q and a buffer 7. In the host device 1, the data is inputted to a data input terminal D of a D flip-flop 9, and the read clock of the reference clock generator 3 is inputted to a clock input terminal of the D flip-flop 9. Accordingly, the data is thereby outputted from an output terminal Q of the D flip-flop 9.
In the data transmission mode described above, wherein the read clock and the data are transmitted between the host device 1 and the SD card 2 via a clock transmission wiring 10 and a data transmission wiring 11, a phase shift generated between the read clock and the data becomes a problem.
The phase shift is described referring to FIG. 11. FIG. 11a) illustrates a waveform of a reference clock A of the reference clock generator 3. FIG. 11b) illustrates a read clock delayed by an arbitrary phase shift (clock skew) in comparison to the reference clock generated when the read clock was transmitted in the clock transmission wiring 10. FIG. 11c) illustrates data outputted to the data output terminal Q of the D flip-lop 6 of the SD card 2 based on the read clock. FIG. 11d) illustrates data delayed by an arbitrary phase shift generated when the data was transmitted in the data transmission wiring 11. When these phase shifts are generated in the read clock and the data, it becomes impossible to read the data from the SD card 2 at a high speed.
There are conventional technical ideas which were proposed to avoid such an inconvenience, which are a source synchronous system and a common clock turn-around system. The source synchronous system is recited in No. 2000-347993 of the Japanese Patent Applications Laid-Open, and the common clock turn-around system is recited in No. 2008-21038 of the Japanese Patent Applications Laid-Open.
The source synchronous system is described below referring to FIG. 12. According to the source synchronous system, when a host device 1, as a transmitter side, transmits data and a source clock in the same transmission path, a SD card 2, as a receiver side, uses the source clock transmitted thereto as a read clock, and transfers the read clock to the host device 1 via a buffer 12 on the SD-card-2 side and a buffer 13 on the host-device-1 side, bringing the read clock into synchronization with a D flip-flop 9 on the host-device side. Accordingly, the variation of a delay time and a clock skew in the transmission path are controlled. As a result, the data can be transferred fast between the host device 1 and the SD card 2.
The common clock system is described below referring to FIG. 13. According to the common clock system, a reference clock is amplified in a buffer 4, and the amplified reference clock is transmitted as a read clock from a transmitter side (host device 1) to a receiver side (SD card 2) via an outgoing transmission wiring 10a, and, in addition, the read clock is fed back to a receiver 15 of the host device 1 through an incoming transmission wiring 10b on the outgoing transmission wiring 10a so that the fed-back clock is used as a clock for a D flip-flop 9 of the host device 1.
In the source synchronous system, however, it is necessary to additionally provide on the SD-card-2 side a pin terminal 14a for transmitting the source clock to the host-device-1 side, a pin terminal 14b for transmitting the data and a pin terminal 14c for transmitting the read clock from the SD card 2 to a card controller 1. As a result, compatibility with other cards is lost.
In the common clock turn-around system, the outgoing transmission wiring 10b branches from the outgoing transmission wiring 10a, and furthermore a circuit configuration thereby obtained is equivalent to a state which seems as if the SD card 2 was connected to a branch point 10c as a capacitor. Therefore, the reflection of signals is generated due to an impedance mismatch at the branch point 10c. The reflection of signal disturbs a waveform of the read clock, which results in the failure of the fast data transmission. It is a possible solution to provide a constitution for realizing the impedance matching on the host-device-1 side: however, impedance varies between the SD card 2 and other cards. Therefore, the constitution may be applicable to the impedance of a particular SD card 2; however, may not be used for the other cards. As a result, connectivity between the cards and the host device is deteriorated.